This is to advise you that a Design and/or Process Change will be made to the following High Reliability product(s):
Product ID (Description): S Level FACT, FAST, LPS, and TTL Logic Products - QML Class V, JAN Class S, and MLS (Exceptions are noted in "Description of Change")
Proposed Date of Change: August 1998
Description of Change: TEST OPTIMIZATION OF SEM WAFER SAMPLING PLAN National Semiconductor's TRB and DSCC have approved changes to the SEM wafer sampling plan used by Fairchild Semiconductor as a supplier of National's S Level logic die. The previous sampling plan, based upon Mil-Std-883 Test Methods 2018 and 5007,specified that two wafers per metal layer must be pulled for SEM inspection on each S Level wafer lot. Since SEM inspection is a destructive test and most logic products use dual layer metal, typically four wafers were sacrificed per wafer lot. The new sampling plan reduces the number of SEM wafers per metal layer from two to one.
Analysis of SEM step coverage data from FACT, FAST, LPS, and TTL wafers showed that these processes have step coverage results that are consistently above the limits and with small enough variation that a reduction in wafer sample size is justified. Along with the one wafer sample, a control limit and a corrective action procedure will be implemented to ensure that S Level wafer lots continue to meet Test Method 2018 step coverage requirements. In the unlikely event that the SEM wafer fails the control limit, the corrective action procedure will reactivate the two wafer sample. Successive failures would require continued use of the two wafer sample until the SEM data supports returning to the one wafer sample. Currently this change applies to FAST single layer metal products (gates) and to the top layer metal on FAST dual layer metal products (buffers, flip-flops, transceivers, multiplexers, etc.), but not to the bottom layer metal on FAST dual layer metal products. The bottom layer metal will be covered when the SEM data supports this change. This change also does not apply to any S Level ECL products.
Effect of Change: There will be no effect on product form, fit, function, or quality. This change will only reduce the number of SEM photos and step coverage measurements provided in the Wafer Lot Acceptance report.
Associated Notes / Table(s):
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